In recent years, trends in the microelectronic industry indicate that future multiprocessor chips may be composed of tens or even hundreds of nodes. A node can be a processing element also called a core and other devices such as caches, input/output, and memory. A desirable feature is that an on-chip broadcast bus provides any one node communication with all nodes on the chip, which is called “any-to-all” communication. In principle, any node which can drive the bus can broadcast information over the bus to all nodes that tap the bus. For example, a broadcast can be used to maintain coherency of any given core's cache.
As the number of nodes increases the bus must scale accordingly. At the same time performance improvements in the node itself require an equivalent increase in bandwidth from the bus. The larger node count leads to greater interconnect path lengths which in turn lead to, greater signal integrity issues, increased chip area requirements, and higher power. These factors, combined with the requirement for higher bandwidth to match the node performance, make the implementation of large scale on chip electronic broadcast buses impractical for high node count, high performance chips.
To overcome these limitations, hierarchical buses have been proposed, such as a bus connected to eight nodes, and sets of buses connected with peer-to-peer links. See e.g., “Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads, and Scaling,” by R. Kumar, V. Zyuan, and D. M. Tullsen, SIGARCH Computer Architecure News 33, 2, pp. 408-419 (May 2005). However, in general, most electrical multi-core processor solutions avoid broadcast interconnects altogether in favor of one-to-one interconnects, such as a mesh. Where broadcast functionality is necessary, broadcast messages are broken down into identical one-to-one messages for each core. While this functionally works for many systems, the redundancy consumes extra bandwidth and power and leads to latency.
An optical bus promises a much higher bandwidth, lower power and lower latency when compared to an electrical bus. However, even with optics, one-to-all bus configurations made up of a number of fixed-sender broadcast buses do not scale well with respect to power and surface area, because as many buses as senders are needed.
Accordingly, an optical, scalable broadcast bus that exhibits low-latency and high-bandwidth is desired. In particular, an on-chip version of such an optical, scalable bus is highly desirable.